MATRIXSYNTH: New Bugbrand Dual Divide & Logic Modules

Wednesday, June 05, 2019

New Bugbrand Dual Divide & Logic Modules

"Dual Divide - This clocking module features two joined integer dividers, offering divisions from 2 through to 9, and capable of running at audio rates.

The clock source can be selected from either the external Clk socket or internal Bus (to be further developed). Divider B can alternately be clocked from the output of Divider A to allow longer divisions. Reset comes from the Rst socket, internal Bus or manual push-button. Both Clock and Reset pass through input comparators with threshold c.+1V. Outputs are 0V low, c.+10V high.

Checking the timing diagram, you can see that clocking occurs on the rising edge of a clock and outputs are high for 1 out of N clock cycles, where N is the Division selected. A Reset event sends both outputs high.

Size: 1FW
Current: +ve 15mA, -ve 0mA"

'Logic Module - This features four utility processors for clock/gate signals.

At the top are two single input processors which can each be set to either invert or divide by two (flip-flop).

Underneath are two twin input logic gates offering AND, OR or XOR responses as shown below:

In 1 In 2 AND OR XOR
0 0 0 0 0
1 0 0 1 1
0 1 0 1 1
1 1 1 1 0

All inputs pass through comparators with threshold c.+1V and can be run at audio rates.
Outputs are 0V low, c.+10V high.

Size: 1FW
Current: +ve 30mA, -ve 0mA"

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